Conventionally, an analog image signal processing circuit such as a mobile phone camera and a digital still camera generally uses a single-ended structure and a differential structure in order to remove common mode noise such as disturbance. An output signal of an image sensor such as a CCD (Charge Coupled Device) and a CMOS (Complementary Metal-Oxide Semiconductor) sensor is sampled by a correlated double sampling circuit and then transmitted to an amplifier of a subsequent stage.
In recent image sensors having improved resolution and higher read frequency, high quality image signal processing is difficult due to degraded S/N (Signal-to-Noise ratio) when high frequency noise is superimposed on a sensor output signal.
FIG. 7 shows a structure of a conventional correlated double sampling circuit. FIG. 8 is a timing chart of the conventional correlated double sampling circuit.
In FIG. 7, 103, 104, and 107 through 116 indicate switch elements, 117 and 118 indicate feedback capacitors, 119 and 120 indicate input terminals, 122 and 123 indicate output terminals, 125 indicates an operational amplifier, 121 indicates an input terminal, 124 indicates an output terminal, and 701 and 702 indicate sampling capacitors.
As shown in FIG. 7, a voltage VOB of a feed-through portion of an image sensor output signal is applied to an input terminal 119, and a voltage VData of a data portion of the image sensor output signal is applied to an input terminal 120. As shown in FIG. 8, the feed-through portion is sampled at a sampling point 801 and the data portion is sampled at a sampling point 802.
In the case where high frequency noise is superimposed on the image sensor output signal, an output voltage ΔVo of the correlated double sampling circuit is shown by the following formula (1), where ΔVOB is a high frequency noise level of the feed-through portion at the sampling point 801, ΔVData is a high frequency noise level of the data portion at the sampling point 802, Voutp is a voltage at an output terminal 122, Voutn is a voltage at an output terminal 123, Cs is a capacitance value of sampling capacitors 701 and 702, and Cf is a capacitance value of feedback capacitors 117 and 118:
                    [                  Formula          ⁢                                          ⁢          1                ]                                                                      Δ          ⁢                                          ⁢                      V            o                          =                                            V              outn                        -                          V              outp                                =                                                    C                s                                            C                f                                      ⁢                                          {                                                                                                                              (                                                                                    V                              Data                                                        -                                                          V                              OB                                                                                )                                                +                                                                                                                                                (                                                                              Δ                            ⁢                                                                                                                  ⁢                                                          V                              Data                                                                                -                                                      Δ                            ⁢                                                                                                                  ⁢                                                          V                              OB                                                                                                      )                                                                                            }                            .                                                          (        1        )            
It can be seen from the formula (1) that the high frequency noise level ΔVOB of the feed-through portion of the image sensor output signal and the high frequency noise level ΔVData of the data portion of the image sensor output signal are multiplied by Cs/Cf and S/N is degraded.
Patent document 1 discloses a method for reducing high frequency noise of an image sensor output signal by inserting a low pass filter between an image sensor and a correlated double sampling circuit.
Patent document 2 discloses a method for reducing a high frequency noise level of a sensor signal by increasing the number of sampling circuits. A sensor signal is thus sampled at a plurality of sampling points and an average value of a plurality of sampling values obtained by the sampling is obtained, whereby a high frequency noise level is reduced.
Patent document 1: Japanese Laid-Open Patent Publication No. 5-68210
Patent document 2: Japanese Laid-Open Patent Publication No. 2005-167790